JFETs

Junction FET (JFET) is the simplest of FETs. JFETs comprise a semiconductor channel embedded into semiconductor layers of opposite polarity. Depending upon whether the semiconductor channel is an n-type semiconductor or a p-type semiconductor, JFETs are classified as n-channel or p-channel JFETs, respectively

Figure below shows the cross-sectional view of an n-channel JFET. N-channel JFET has an n-type semiconductor material that forms a channel between embedded layers of p-type material.

Cross-section of an n-channel JFET

Figure below shows the cross-sectional view of a p-channel JFET. Here a p-type semiconductor forms a channel between the embedded layers of n-type material.

Cross-section of a p-channel JFET

Therefore, in both the types of JFETs, two P-N junctions are formed between the semiconductor channel and the embedded semiconductor layers. Ohmic contacts are made at the top and bottom of the channel. They are referred to as the drain (D) and the source (S) terminals, respectively. The channel behaves as a resistive element between its drain and source terminals. In an n-channel JFET, both the embedded p-type layers are connected together to form the gate (G) terminal. Similarly in a p-channel JFET, both the n-type embedded layers are connected together to form the gate (G) terminal. In the absence of any externally applied potential, both the P-N junctions are open circuit. Hence, a small depletion region is formed at each of the junctions as shown in figures above. The externally applied potential between G and S terminals controls the flow of drain current for a given potential between the D and S terminals.

Figure below shows the circuit symbol of an n-channel JFET.

Figure below shows circuit symbol of a p-channel JFET.

Figure below shows circuit symbol of a p-channel JFET.

Circuit symbol of a p-channel JFET

Working of n-channel JFET is explained here. The operation of a p-channel JFET is similar to that of an n-channel JFET with the polarities of voltages and direction of currents reversed. The circuit is explained below under different conditions.
1. Positive drain-source voltage (V_DS) with gate terminal shorted to the source terminal (V_GS= 0). Figure below shows the circuit connection.

n-channel JFET with V_GS = 0 and positive value of V_DS

When positive drain-source voltage is applied, the electrons in the n-channel are attracted to the drain-terminal establishing the flow of drain current (ID). The value of ID depends on the value of the applied V_DS and the resistance of the n-channel between the drain and the source terminals. Due to the flow of ID, there is a uniform voltage drop across the channel resistance. This reverse-biases the two P-N junctions and hence there is an increase in the width of the depletion region. Depletion region is wider near the drain-region than the source-region because ID and the channel resistance establish more reverse-bias voltage at the P-N junction near the drain-region as compared to that near the source-region.

n-channel JFET with V_GS= 0 and positive value of V_DS

ID increases linearly with increase in V_DS till the V_DS reaches a value where the saturation effect sets in. This value of V_DS where the saturation effect sets in is referred to as the pinch-off voltage (VP). After V_DS equals VP, the value of ID does not change with further increase in the value of V_DS. This condition is referred to as the pinch-off condition and the value of drain current is referred to as the drain-to-source current for short circuit connection between gate and source (IDSS). Figure below shows the ID versus V_DSfor V_GS = 0 curve.

ID versus V_DS for V_GS = 0

Pinch-off happens because the width of the depletion regions of the P-N junctions has increased significantly near the D-region resulting in reduction of the channel width as shown in figure below. Therefore, ID is equal to IDSS and essentially remains constant for V_DS > VP. In nutshell, for V_DS > VP, JFET has characteristics of a constant current source.

n-channel JFET with V_GS = 0 and V_DS VP

2. Both drain and gate voltages are applied to the JFET For an n-channel JFET, negative V_GS is applied to the FET, whereas for p-channel JFETs,V_GS is positive. Figure below shows the circuit connection when both drain and gate voltages are applied to the JFET.

n-channel JFET biasing circuit

When a negative bias is applied to the gate terminal, it is reverse biased. Hence, there is an increase in the width of the depletion region. Therefore, the pinch-off phenomenon occurs at lower values of V_DS and the value of saturation drain current decreases. As the value of V_GS becomes more negative, the value of saturation current further decreases. The drain current becomes zero for V_GS equal to –VP. This voltage is referred to as the gate-source cut-off voltage or the gate-source pinch-off voltage (V_GS(off)). The value of drain-source pinch-off voltages decreases in a parabolic manner with theV_GS becoming more negative.

Figure below shows the output characteristic curves for the n-channel JFET.

Output characteristic curves of an n-channel JFET

The different regions are explained below. • The region to the left of the locus of pinch-off voltages is the Ohmic region or the voltage-controlled resistance region. The JFET acts as a variable resistor in this region whose resistance is controlled by the applied gate-source voltage.
• Region to the right of the locus of the pinch-off voltages is the saturation region or the constant-current region. Here the current ID remains constant.

The drain resistance (rd) in the saturation region is given by

Where,
ro is the resistance at V_GS = 0 rd is the resistance at a particular value of V_GS Vp is the pinch-off voltage

There is a non-linear square law relationship between the output drain current ID and the input gate-source voltage V_GS in the saturation region. The relationship is expressed as

Where,
IDSS is the drain current for short circuit connection between gate and source This expression is referred to as the Shockley’s equation.

JFETs are used in radio tuners and TV receivers due to the square law relationship between ID and V_GS.

Transfer characteristic curves of n-channel JFET

. Figure below shows the output characteristic curves for p-channel JFETs. We can see from the figure that the curves for the p-channel JFETs are the same as for n-channel JFETs except that the direction of currents and polarities of voltages are reversed.

Characteristic curve of p-channel JFET

Increase in JFET temperature results in decrease in the values of the following two parameters
a. Depletion region width.
b. Carrier mobility. Decrease in the width of the depletion region results in increase in channel width, which in turn increases ID. This results in positive temperature coefficient for ID. Increase in ID with temperature results in increase in V_GS(off) with temperature. Therefore, V_GS(off) also has a positive temperature coefficient of the order of 2.2 mV/^°C. Decrease in carrier mobility gives ID a negative temperature coefficient. Since both the mechanisms occur simultaneously, the effect of one mechanism compensates for the other. Therefore, JFETs offer better temperature stability. It is even possible to bias the JFET so as to establish zero temperature coefficient of ID.